The present invention relates to controller LSIs (Large Scale Integrated circuits) controlling peripheral devices having a power down mode and information processing systems equipped with the controller LSIs, and more particularly to a controller LSI capable of putting itself into low power consumption mode and being suitably applicable to an information processing system.
With recent society-wide efforts to improve energy efficiency, ensuring low power consumption of semiconductor systems is almost an indispensable requirement. There are an increasing number of products provided with a low power consumption mode; the products include not only microcomputers with a CPU (Central Processing Unit), but also external peripheral devices, such as RAMs (Random Access Memories) and ROMs (Read Only Memories). As to external ROMs, migration from generally-used simultaneously-accessible parallel NOR-flash memories (registered trademark) (NOR-Flash) to SPI NOR-Flash memories that can perform the equivalent functions to those of the generally-used NOR flash memories with fewer pins is underway. In order to perform the equivalent functions with fewer pins, the SPI NOR-Flash is designed to gain access, on a command base, through a communication channel of SPI (Serial Peripheral Interface) communication, which is one of the communication modes among on-board ICs (Integrated Circuits). Recent devices have a low power consumption mode function, so-called deep power down (DPD) mode (DPM) that is also executable on a command base. In response to a deep power down command (DP command), the devices enter deep power down mode, while returning from the deep power down mode to normal mode in response to a RES (REleaSe from Deep Power Down) command. LSI is increasingly required to implement a function for manipulating the low power consumption mode function as a controller.
Japanese Unexamined Patent Publication No. 2010-55419 discloses a technology of reducing power consumption of a NOR flash memory. The NOR flash memory has a DPD function that brings the NOR flash memory into deep power down mode to reduce power consumption and enters and returns from the DPD state in response to a DPD signal supplied from a memory control unit connected thereto. The memory control unit brings the NOR flash memory into a DPD state when the memory control unit does not receive a request to access the NOR flash memory within a predetermined period of time.